Phase 3: Circuit Validation with PySpice and Lcapy

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feat: add rlc series circuit json file and remove yaml version
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#102 by fuzzy was merged 2026-05-04 04:41:03 +00:00
phase03/validation
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#101 by fuzzy was merged 2026-05-04 04:28:52 +00:00
feat: add series rlc circuit definition in yaml format
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#100 by fuzzy was merged 2026-05-04 04:02:20 +00:00
phase03/validation
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#99 by fuzzy was merged 2026-05-03 22:41:24 +00:00
feat: add schematic generation to skidl scripts and update kicad-cli export logic
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#97 by fuzzy was merged 2026-05-03 13:39:19 +00:00
phase03/validation
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#96 by fuzzy was merged 2026-05-03 13:35:27 +00:00
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#21 by fuzzy was closed 2026-05-03 13:35:28 +00:00