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Phase 6: Polish and Extensibility
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Phase 1: Project Foundation and Configuration
Phase 2: SKiDL Netlist Generation
Phase 3: Circuit Validation with PySpice and Lcapy
Phase 4: Automation Workflow and Integration
Phase 5: Documentation and Testing
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fuzzy
the.auditor
fix: update schematic generation to use retries instead of auto_stub
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#121 by fuzzy was merged 2026-05-05 14:30:55 +00:00
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refactor: extract skidl circuit building into separate function and improve schematic generation fallback logic
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#120 by fuzzy was merged 2026-05-05 14:19:17 +00:00
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feat: enhance schematic generation with routing and improved error handling
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#119 by fuzzy was merged 2026-05-05 10:45:34 +00:00
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feat: add schematic image generation for circuits
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#118 by fuzzy was merged 2026-05-05 10:37:20 +00:00
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fix: simplify kicad symbols installation in workflow
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#117 by fuzzy was merged 2026-05-05 10:21:13 +00:00
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fix: update kicad symbols installation to use wget and dpkg-deb
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#116 by fuzzy was merged 2026-05-05 10:18:09 +00:00
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fix: update transistor symbol mapping to Q_NPN_BCE
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#115 by fuzzy was merged 2026-05-05 09:04:55 +00:00
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fix: update connector symbol mappings to generic connector types
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#114 by fuzzy was merged 2026-05-05 08:36:34 +00:00
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chore: trigger workflow on merge.yml changes
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#113 by fuzzy was merged 2026-05-05 08:22:49 +00:00
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feat: add colorsound overdrive guitar effect circuit definition
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#112 by fuzzy was merged 2026-05-05 07:56:14 +00:00
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feat: add JRC4558 opamp to skidl mapper
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#111 by fuzzy was merged 2026-05-05 07:46:26 +00:00
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feat: add pigbutt overdrive circuit definition with full netlist
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#110 by fuzzy was merged 2026-05-05 07:36:31 +00:00
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feat: convert inverting amplifier circuit to yaml format
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#109 by fuzzy was merged 2026-05-05 05:47:25 +00:00
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phase06/final-touches
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#108 by fuzzy was merged 2026-05-05 05:44:28 +00:00
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Phase 6: Polish and Extensibility
docs: add project README with quick start and overview
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#107 by fuzzy was merged 2026-05-05 05:14:40 +00:00
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Phase 5: Documentation and Testing
phase05/documentation
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#106 by fuzzy was merged 2026-05-05 05:06:32 +00:00
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Phase 5: Documentation and Testing
feat: add series RLC circuit with YAML format and updated BOM components
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#105 by fuzzy was merged 2026-05-04 07:54:35 +00:00
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feat: post PR comment with artifact generation summary
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#104 by fuzzy was merged 2026-05-04 07:52:05 +00:00
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Phase 4: Automation Workflow and Integration
feat: update roadmap with completed automation workflow and tests
#103 by fuzzy was merged 2026-05-04 06:07:01 +00:00
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feat: add rlc series circuit json file and remove yaml version
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#102 by fuzzy was merged 2026-05-04 04:41:03 +00:00
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Phase 3: Circuit Validation with PySpice and Lcapy