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phase02/netlist #72

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fuzzy merged 8 commits from phase02/netlist into main 2026-05-03 10:06:29 +00:00
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fuzzy commented 2026-05-03 09:55:02 +00:00
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Add skidl_mapper module that transforms circuit BOM entries into
SKiDL Part constructors in a generated Python script.

Also add skidl dependency, update ROADMAP, and fix .gitignore.

closes: #11
Add targeted tests for net variable declarations, connection
line generation, pin quoting rules, and connection count validation.

closes: #12
Add script structure tests verifying section ordering, component
preservation, footprint inclusion, and Python parseability.

closes: #13
closes: #14
Add generator module with SKiDL script execution, BOM CSV generation,
footprint handling, and KiCad CLI schematic generation wrapper.

closes: #15
closes: #17
closes: #19
closes: #20
fix: quote library names in generated SKiDL Part constructors
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fba8b09f67 
SKiDL Part() requires string arguments for library and part names.
Also mark Phase 2 complete in ROADMAP.

closes: #16
closes: #18
fuzzy force-pushed phase02/netlist from fba8b09f67
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to a62476a31e
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2026-05-03 09:55:11 +00:00 Compare
chore: remove inverting amplifier and RLC series circuit definitions
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0d4a2f4c05 
# Previous message:
chore: remove inverting amplifier and RLC series circuit files

# Previous message:
chore: remove inverting amplifier and RLC series circuit files
fix: auto-detect circuit file format (YAML or JSON)
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936a7dd176 
Add find_circuit_file() helper and update all tests to use it
instead of hardcoding paths, so removing one format works.
ci: trigger on PR only, add merge workflow for artifact generation
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9e036c878a 
ci.yml now only triggers on pull_request, merge.yml triggers on merge
to main and commits generated artifacts back to the branch.
fuzzy merged commit 9e036c878a into main 2026-05-03 10:06:29 +00:00
fuzzy deleted branch phase02/netlist 2026-05-03 10:06:29 +00:00
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